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HT1623
RAM Mapping 488 LCD Controller for I/O MCU
Features
* Operating voltage: 2.7V~5.2V * Built-in RC oscillator * External 32.768kHz crystal or 32kHz frequency * Built-in LCD display RAM * R/W address auto increment * Two selection buzzer frequencies (2kHz or 4kHz) * Power down command reduces power consumption * Software configuration feature * Data mode and Command mode instructions * Three data accessing modes * VLCD pin to adjust LCD operating voltage * Cascade application * 100-pin QFP package
source input
* 1/4 bias, 1/8 duty, frame frequency is 64Hz * Max. 488 patterns, 8 commons, 48 segments * Built-in internal resistor type bias generator * 3-wire serial interface * 8 kinds of time base or WDT selection * Time base or WDT overflow output
General Description
HT1623 is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 384 patterns (488). It also supports serial interface, buzzer sound, watchdog timer or time base timer functions. The HT1623 is a memory mapping and multi-function LCD controller. The software configuration feature of the HT1623 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only three lines are required for the interface between the host controller and the HT1623. The HT162X series have many kinds of products that match various applications.
Selection Table
HT162X COM SEG Built-in Osc. Crystal Osc. HT1620 4 32 3/4 O HT1621 4 32 O O HT1622 8 32 O 3/4 HT16220 8 32 3/4 O HT1623 8 48 O O HT1625 8 64 O O HT1626 16 48 O O
Block Diagram
OSCO OSCI CS RD WR DATA VDD VSS BZ BZ T o n e . re q u e n c y G e n e ra to r C o n tro l and T im in g C ir c u it
D is p la y R A M
COM0 L C D D r iv e r / B ia s C ir c u it COM7 SEG0 SEG 47 VLCD W a tc h d o g T im e r and T im e B a s e G e n e r a to r IR Q
Rev. 1.10
1
September 11, 2002
HT1623
Pin Assignment
SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4445 46 4748 49 50 100 99 98 97 96 9594 93 92 91 90 89 88 87 86 8584 83 82 81 N N N G3 G3 G3 G3 G3 G3 G3 G3 G4 G4 G4 G4 G4 G4 G4 G4 N C C C C 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 80 79 78 77 76 75 74 73 72 71 70 69 68 NC NC NC NC NC NC NC SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE SE NC NC NC NC G3 G3 G2 G2 G2 G2 G2 G2 G2 G2 G2 G2 G1 G1 G1 G1 G1 G1 G1 3 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 CS RD WR DATA VSS OSCI OSCO VDD VLC D IR Q BZ BZ T1 T2 T3 COM0 COM1 NC NC NC NC NC NC NC NC NC NC COM2 COM3 COM4
H T1623 1 0 0 Q . P -A
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
NC NC NC NC SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG SEG COM COM COM 0 12 11 10 1 2 3 4 5 6 7 8 9 5 6 7
Rev. 1.10
2
September 11, 2002
HT1623
Pad Assignment
SEG 47 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 COM3 20 COM4 21 COM5 22 COM6 23 COM7 24 SEG0 25 SEG1 26 SEG2 27 SEG3 28 SEG4 29 SEG5 30 SEG6 31 SEG7 32 SEG8 33 SEG9 34 SEG 10 35 SEG 11 36 SEG 12 37 SEG 13 (0 ,0 ) 71 SEG 46 70 SEG 45 69 SEG 44 68 SEG 43 67 SEG 42 66 SEG 41 65 SEG 40 64 SEG 39 63 SEG 38 62 SEG 37 61 SEG 36 60 SEG 35 59 SEG 34 58 SEG 33 57 SEG 32 56
CS RD WR DATA VSS OSCI OSCO VDD VLCD IR Q BZ BZ T1 T2 T3 COM0 COM1 COM2
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38
SEG 31 SEG 30 SEG 29 SEG 28 SEG 27 SEG 26 SEG 25 SEG 24 SEG 23 SEG 22 SEG 21 SEG 20 SEG 19 SEG 18 SEG 17 SEG 16 SEG 15 SEG 14
Chip size: 177 171 (mil)2 * The IC substrate should be connected to VDD in the PCB layout artwork.
Rev. 1.10
3
September 11, 2002
HT1623
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 X -82.45 -82.45 -82.45 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -83.21 -82.88 -72.50 -65.88 -59.24 -52.62 -45.73 -33.32 -26.69 -14.28 -7.65 4.76 11.39 23.80 30.43 42.84 49.47 61.88 68.51 80.92 Y 79.35 67.02 60.39 46.71 32.30 25.20 18.57 11.94 5.31 -4.84 -16.66 -29.92 -41.74 -48.37 -54.99 -61.63 -68.25 -78.96 -79.99 -79.99 -79.99 -79.99 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 -79.22 Pad No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 X 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 82.83 27.03 20.40 13.77 7.14 0.51 -6.12 -12.75 -19.38 -26.01 -32.64 -39.27 -45.90 -52.53 -59.16 -65.79 -72.42 Y -52.44 -35.23 -28.60 -21.97 -15.34 -8.71 -2.08 4.55 11.18 17.81 24.44 31.07 37.70 44.33 50.96 57.59 64.22 70.85 77.48 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 79.35 Unit: mil
Rev. 1.10
4
September 11, 2002
HT1623
Pad Description
Pad No. Pad Name I/O Description Chip selection input with pull-high resistor. When the CS is logic high, the data and command read from or written to the HT1623 are disabled. The serial interface circuit is also reset But if the CS is at logic low level and is input to the CS pad, the data and command transmission between the host controller and the HT1623 are all enabled. READ clock input with pull-high resistor. Data in the RAM of the HT1623 are clocked out on the falling edge of the RD signal. The clocked out data will appear on the data line. The host controller can use the next rising edge to latch the clocked out data. WRITE clock input with pull-high resistor. Data on the DATA line are latched into the HT1623 on the rising edge of the WR signal. Serial data input or output with pull-high resistor Negative power supply, ground The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to generate a system clock. If the system clock comes from an external clock source, the external clock source should be connected to the OSCI pad. But if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads can be left open. Positive power supply LCD operating voltage input pad. Time base or watchdog timer overflow flag, NMOS open drain output 2kHz or 4kHz tone frequency output pair Not connected LCD common outputs LCD segment outputs
1
CS
I
2
RD
I
3 4 5 6
WR DATA VSS OSCI
I I/O 3/4 I
7
OSCO
O 3/4 I O O I O O
8 9 10 11, 12 13~15 16~23 24~71
VDD VLCD IRQ BZ, BZ T1~T3 COM0~COM7 SEG0~SEG47
Absolute Maximum Ratings
Supply Voltage .........................................-0.3V to 5.5V Input Voltage.............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.10
5
September 11, 2002
HT1623
D.C. Characteristics
Symbol VDD IDD1 Parameter Operating Voltage Operating Current 5V IDD2 3V Operating Current 5V IDD11 3V Operating Current 5V IDD22 3V Operating Current 5V ISTB 3V Standby Current 5V VIL 3V Input Low Voltage 5V VIH 3V Input High Voltage 5V IOL1 3V BZ, BZ, IRQ 5V IOH1 3V BZ, BZ 5V IOL1 3V DATA 5V IOH1 3V DATA 5V IOL2 3V LCD Common Sink Current 5V IOH2 3V LCD Common Source Current 5V IOL3 3V LCD Segment Sink Current 5V IOH3 3V LCD Segment Source Current 5V RPH 3V Pull-high Resistor 5V DATA, WR, CS, RD 50 100 150 kW VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V VOL=0.3V VOL=0.5V VOH=2.7V VOH=4.5V DATA, WR, CS, RD 4.0 0.9 1.7 -0.9 -1.7 0.9 1.7 -0.9 -1.7 80 180 -40 -90 50 120 -30 -70 100 DATA, WR, CS, RD 0 2.4 No load, Power down mode Test Conditions VDD 3/4 3V Conditions 3/4 No load or LCD ON On-chip RC oscillator No load or LCD ON Crystal oscillator No load or LCD OFF On-chip RC oscillator No load or LCD OFF Crystal oscillator Min. 2.7 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0 Typ. 3/4 155 260 150 250 8 20 3/4 3/4 1 2 3/4 3/4 3/4 3/4 1.8 3 -1.8 -3 1.8 3 -1.8 -3 160 360 -80 -180 100 240 -60 -140 200 Max. 5.2 310 420 310 420 30 60 20 35 10 20 0.6 1.0 3 5 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 300 Ta=25C Unit V mA mA mA mA mA mA mA mA mA mA V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA kW
Rev. 1.10
6
September 11, 2002
HT1623
A.C. Characteristics
Symbol fSYS1 fSYS2 fLCD1 fLCD2 tCOM fCLK1 fCLK2 tCS System Clock System Clock LCD Frame Frequency LCD Frame Frequency LCD Common Period Serial Data Clock (WR Pin) Parameter Test Conditions VDD 3V 5V 3V 5V 3V 5V 3V 5V 3/4 3V 5V 3V 5V 3/4 3V tCLK WR, RD Input Pulse Width (Figure 1) 5V tr, tf tsu th tsu1 th1 Rise/Fall Time Serial Data Clock Width (Figure 1) Setup Time DATA to WR, RD Clock Width (Figure 2) Hold Time DATA to WR, RD Clock Width (Figure 2) Setup Time for CS to WR, RD Clock Width (Figure 3) Hold Time for CS to WR, RD Clock Width (Figure 3) 3V 5V 3V 5V 3V 5V 3V 5V 3V 5V Conditions On-chip RC oscillator External clock source On-chip RC oscillator External clock source n: Number of COM Duty cycle 50% Min. 22 24 3/4 3/4 44 48 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3.34 6.67 1.67 3.34 3/4 3/4 3/4 3/4 3/4
V A L ID D A T A
Ta=25C Typ. 32 32 32 32 64 64 64 64 n/fLCD 3/4 3/4 3/4 3/4 250 3/4 3/4 3/4 3/4 120 120 120 100 100 Max. 40 40 3/4 3/4 80 80 3/4 3/4 3/4 150 300 75 150 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 Unit kHz kHz kHz kHz Hz Hz Hz Hz sec kHz kHz kHz kHz ns ms ms ns ns ns ns ns
Serial Data Clock (RD Pin) Serial Interface Reset Pulse Width (Figure 3)
Duty cycle 50% CS Write mode Read mode Write mode Read mode 3/4 3/4 3/4 3/4 3/4
tf W R,RD C lo c k 90% 50% 10%
tr
-V tC
LK
DD
DB
V th
DD
50% ts
u
GND V
DD
tC
LK
GND
W R,RD C lo c k
50%
-G N D
Figure 1
tC
S
Figure 2
CS
50% ts
u1
-V
DD
th
1
GND -V
DD
W R,RD C lo c k
50% . IR S T C lo c k
LAST C lo c k
GND
Figure 3
Rev. 1.10
7
September 11, 2002
HT1623
Functional Description
Display memory - RAM structure The static display RAM is organized into 964 bits and stores the display data. The contents of the RAM are directly mapped to the contents of the LCD driver. Data in the RAM can be accessed by theREAD, WRITE and READ-MODIFY-WRITE commands. The following is a mapping from the RAM to the LCD patterns. Time base and watchdog timer - WDT The time base generator and WDT share the same divided (/256) counter. TIMER DIS/EN/CLR, WDT DIS/EN/CLR and IRQ EN/DIS are independent from each other. Once the WDT time-out occurs, the IRQ pin will remain at logic low level until the CLR WDT or the IRQ DIS command is issued.
COM7 SEG0 SEG1 SEG2 SEG3 7 5 6 3 4 A d d r e s s 7 B its (A 6 , A 5 , ...., A 0 ) COM6 COM5 COM4 1 2
If an external clock is selected as the source of system frequency, the SYS DIS command turns out invalid and the power down mode fails to be carried out until the external clock source is removed. Buzzer tone output A simple tone generator is implemented in the HT1623. The tone generator can output a pair of differential driving signals on the BZ and BZ which are used to generate a single tone. Command format The HT1623 can be configured by the software setting. There are two mode commands to configure the HT1623 resource and to transfer the LCD display data.
COM3 COM2 COM1 COM0 0
SEG 47 D3 D2 D1 D0
95 Addr D a ta D3 D2 D1 D0
94 Addr D a ta
D a ta 4 B its (D 3 , D 2 , D 1 , D 0 )
RAM mapping
T im e B a s e C lo c k S o u r c e /2 5 6 V C L R T im e r
DD
T IM E R
E N /D IS
IR Q
W D T E N /D IS D CK R Q IR Q E N /D IS
W DT /4
CLR
W DT
Timer and WDT configurations
Rev. 1.10
8
September 11, 2002
HT1623
The following are the data mode ID and the command mode ID: Operation READ WRITE READ-MODIFY-WRITE COMMAND Name TONE OFF TONE 4K TONE 2K Mode Data Data Data Command Command Code 0000-1000-X 010X-XXXX-X 0110-XXXX-X Turn-off tone output Turn-on tone output, tone frequency is 4kHz Turn-on tone output, tone frequency is 2kHz ID 110 101 101 100 Function If successive commands have been issued, the command mode ID can be omitted. While the system is operating in the non-successive command or the non-successive address data mode, the CS pin should be set to 1 and the previous operation mode will be reset also. The CS pin returns to 0, a new operation mode ID should be issued first.
Timing Diagrams
READ mode (command code : 1 1 0)
CS
WR
RD
DATA
1 1
0
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3 1
1
0
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
READ mdoe (successive address reading)
CS
WR
RD
DATA
1 1
0
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 2 )
D a ta (M A + 3 )
Rev. 1.10
9
September 11, 2002
HT1623
WRITE mode (command code : 1 0 1)
CS
WR
DATA
1 0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3 1
0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
WRITE mode (successive address writing)
CS
WR
DATA
1 0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 2 )
D a ta (M A + 3 )
READ-MODIFY-WRITE mode (command code : 1 0 1)
CS
WR
RD
DATA
1 0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3 1
0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
M e m o ry A d d re s s 1 (M A 1 )
D a ta (M A 1 )
D a ta (M A 1 )
M e m o ry A d d re s s 2 (M A 2 )
D a ta (M A 2 )
READ-MODIFY-WRITE mode (successive address accessing)
CS
WR
RD
DATA
1 0
1
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
D1
D2
D3
D0
M e m o ry A d d re s s (M A )
D a ta (M A )
D a ta (M A )
D a ta (M A + 1 )
D a ta (M A + 1 )
D a ta (M A + 2 )
Rev. 1.10
10
September 11, 2002
HT1623
Command mode (command code : 1 0 0)
CS
WR
DATA
1 0
0
C8
C7
C6
C5
C4
C3
C2
C1
C0 C o m m a n d ...
C8
C7
C6
C5
C4
C3
C2
C1
C0 Com m and or D a ta M o d e
Com m and 1
Com m and i
Mode (data and command mode)
CS
WR
DATA
Com m and or D a ta M o d e
A d d re s s a n d D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
Com m and or D a ta M o d e
A d d re s s a n d D a ta
RD
Rev. 1.10
11
September 11, 2002
HT1623
Application Circuits
*
CS RD WR
VDD *V R VLCD
MCU
*R
DATA
H T1623
BZ P ie z o BZ
IR Q OSCI C lo c k O u t E x te r n a l C lo c k 1 ( 3 2 k H z ) E x te r n a l C lo c k 2 ( 3 2 k H z ) O n - c h ip O S C OSCO COM0~COM7 SEG 0~SEG 47
1 /4 B ia s , 1 /8 D u ty
LCD
Panel
C ry s ta l 32768H z
Note:
The connection of IRQ and RD pin can be selected depending on the requirement of the MCU. The voltage applied to VLCD pin must be lower than VDD. Adjust VR to fit LCD display, at VDD=5V, VLCD=4V, VR=15kW20%. Adjust R (external pull-high resistance) to fit users time base clock.
Command Summary
Name READ WRITE ID Command Code D/C D D D C C C C C C C C C C C C C C Function Read data from the RAM Write data to the RAM Read and Write data to the RAM Turn off both system oscillator and LCD bias Yes generator Turn on system oscillator Turn off LCD display Turn on LCD display Disable time base output Disable WDT time-out flag output Enable time base output Enable WDT time-out flag output Turn off tone outputs Clear the contents of the time base generator Clear the contents of the WDT stage System clock source, on-chip RC oscillator System clock source, external 32kHz clock source or crystal oscillator 32.768kHz Tone frequency output: 4kHz Yes Yes Yes Yes Yes Def. 1 1 0 A6A5A4A3A2A1A0D0D1D2D3 1 0 1 A6A5A4A3A2A1A0D0D1D2D3
READ-MODIFY1 0 1 A6A5A4A3A2A1A0D0D1D2D3 WRITE SYS DIS SYS EN LCD OFF LCD ON TIMER DIS WDT DIS TIMER EN WDT EN TONE OFF CLR TIMER CLR WDT RC 32K 1 0 0 0000-0000-X 1 0 0 0000-0001-X 1 0 0 0000-0010-X 1 0 0 0000-0011-X 1 0 0 0000-0100-X 1 0 0 0000-0101-X 1 0 0 0000-0110-X 1 0 0 0000-0111-X 1 0 0 0000-1000-X 1 0 0 0000-1101-X 1 0 0 0000-1111-X 1 0 0 0001-10XX-X
EXT (XTAL) 32K 1 0 0 0001-11XX-X TONE 4K 1 0 0 010X-XXXX-X
Rev. 1.10
12
September 11, 2002
HT1623
Name TONE 2K IRQ DIS IRQ EN F1 F2 F4 F8 F16 F32 F64 F128 TEST NORMAL Note: ID Command Code D/C C C C C C C C C C C C C C Function Tone frequency output: 2kHz Disable IRQ output Enable IRQ output Time base clock output: 1Hz The WDT time-out flag after: 4s Time base clock output: 2Hz The WDT time-out flag after: 2s Time base clock output: 4Hz The WDT time-out flag after: 1s Time base clock output: 8Hz The WDT time-out flag after: 1/2s Time base clock output: 16Hz The WDT time-out flag after: 1/4s Time base clock output: 32Hz The WDT time-out flag after: 1/8s Time base clock output: 64Hz The WDT time-out flag after: 1/16s Time base clock output: 128Hz The WDT time-out flag after: 1/32s Test mode, user dont use. Normal mode Yes Yes Yes Def.
1 0 0 0110-XXXX-X 1 0 0 100X-0XXX-X 1 0 0 100X-1XXX-X 1 0 0 101X-0000-X 1 0 0 101X-0001-X 1 0 0 101X-0010-X 1 0 0 101X-0011-X 1 0 0 101X-0100-X 1 0 0 101X-0101-X 1 0 0 101X-0110-X 1 0 0 101X-0111-X 1 0 0 1110-0000-X 1 0 0 1110-0011-X
X : Dont care A6~A0 : RAM address D3~D0 : RAM data D/C : Data/Command mode Def. : Power on reset default All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command mode ID. If successive commands have been issued, the command mode ID except for the first command will be omitted. The source of the tone frequency and of the time base or WDT clock frequency can be derived from an on-chip 32kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 32kHz clock. Calculation of the frequency is based on the system frequency sources as stated above. It is recommended that the host controller should initialize the HT1623 after power on reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1623.
Rev. 1.10
13
September 11, 2002
HT1623
Package Information
100-pin QFP (1420) outline dimensions
C D 80 51 G H
I 81 50
. A B
E
100
31 K 1 30 = J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.50 13.90 24.50 19.90 3/4 3/4 2.50 3/4 3/4 1 0.10 0 Nom. 3/4 3/4 3/4 3/4 0.65 0.30 3/4 3/4 0.10 3/4 3/4 3/4 Max. 19.20 14.10 25.20 20.10 3/4 3/4 3.10 3.40 3/4 1.40 0.20 7
Rev. 1.10
14
September 11, 2002
HT1623
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 0755-8616-9908, 8616-9308 Fax: 0755-8616-9533 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 028-6653-6590 Fax: 028-6653-6591 Holmate Semiconductor, Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright O 2002 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.10
15
September 11, 2002

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